,. analog w devices i features resolution: 12 bits nonlinearity: j: 1/2lsb t mln to t mex 12-bit input register small size: 24 pin dip fast settling: 5fls to j:o.o1% internal reference internal output amplifier product description the ad3860 is a precision 12-bit d/a converter designed for direct interface to microprocessors. the functional diagram shows that the ad3860 consists of a 12- bh input storage register, a 12-bit dac, internal reference, and a fast output amplifier. it is ttl compatible and the register enable facilitates deglitching and microprocessor interfacing. the low noise, high stability subsurface zener diode is used to produce a reference voltage with excellent long term stability, external current capability and temperature drift characteristics. the output amplifier gives the user a voltage output and combines with the other features of this circuit to produce a functionally complete digital to analog converter. ' the ad3860 is laser trimmed to achieve :t 1/4lsb linearity typical and :t 1/2lsb maximum over the full operating temper- ature range. the low t.e. binary ladder guarantees that the ad3860 will be monotonic over the specified temperature range. the ad3860 is available in two versions. the AD3860K is specified for use over 0 to + 70c temperature range. the ad3860s is specified for the - 55c to + 125c temperature range and is especially recommended for high reliability needs in harsh envi- ronments. all units are in supplied in 24-pin, hermetically-sealed ceramic dips. complete, voltage output 12-bit buffered oac ad3860 ..1 ad3860 functional block diagram '"""0'.." 0 "', ~(1t: ":;';';';""'juiocnon' '. '15) voltage output ;. ',' '. product illghlights ' . , .."., 1. the ad3860 is a functionally complete voltage output'dac ' with voltage reference, digital'latches, and output amplifier in a single hybrid package. ' 2. the input buffer latches permit interface to niicroprocessor data buses. all logic inputs are ttl'or 5 voltcmos'com- patible. 3. laser trimming the thin-film resistors assures superior linearity and accuracy stability over temperature. both commercial and military temperature range models have :t 1/2lsb linearity maximum guaranteed over the full operating tempe,rature range. ' , 4. monotonicity is also guaranteed over the full operating tem- perature range. the typical full scale temperature coefficient is loppmrc. s. the precision buried zener reference can supply up to 2.sma for use elsewhere in the application. 6. the fast output amplifier provides a voltage output with a 5fls settling time to 0.01% for a 20 volt step. the ad3860 is designed for military and industrial applications where high speed d/a conversion is required. digital-to-analog converters vol. 1,9-93 ,~...-...._.._... ~_. obsolete
specifications .. .. . (typical @ + 25 "c, rnted pa.yer ~ td!ss o\iewise ooted) model digital inputs resolution logic coding: unipolar ranges bipolar ranges logic levels(tfl compatible): logic "i" logic "0" input currents data inputs: logic" 1" logic "0" register enable: logic "i" logic "0" AD3860K 12 bits complementary straight binary complementary offset binary +2.0vdcmin, +5.5vdcmax ovdcmin,0.8vdcmax joj1a max -0.6mamax 6oij.a max - i.2mamax ad3860s " " " " " " " " analog output output impedance output current @ zl = 2kol1250pf accuracy linearity error ct min to t maj differential linearity error monotonicity full scale absolute accuracy erro.-2 tmin to tmax zero error tmin to tmax gain error drift gain offset dynamic characteristics settling time to :to.oi%for:20vstep 10vstep output slew rate register enable. pulse width setup time digital data to enable internal reference voltage voltage accuracy external current 0.50 :t lama, :tsmamin :tl/4lsb1, :t1l2lsbmax :t 1i2lsb, :t ilsb max guaranteed over temperature :to.05%fsr3, :t 0.1% fsrmax :to.is%fsr, :t 0.3% fsrmax :to.02s%fsr, :to.os%fsrmax :to.05%fsr, :to.i%fsrmax :to.l% :t ioppmt'c :t sppmrc s fls, 7 fls max 3fls, sfls max 20v/lj.s 6ons min 4ons min +6.3v :t2% 2.sma max " " :!: 1/2lsb max :t ilsb " " " " " " " " * * * " " * * " power supplies power supply range: + isv supply -isv supply +5vsupply power supply rejection: + isv supply -i5vsupply current drain: + 15v supply -i5vsupply + 5v supply power consumption temperature range operating storage + 14.5sv min, + is.45v max - 14.55v min, -is.45v max +4.75vmin, +s.2svmax :t 0.002% fsr/% vs :t 0.01% fsr/% vsmax :t 0.002% fsr/% v s :to.oo4%fsr/% vsmax ioma,20mamax - 12ma, - 30ma max 30ma, soma max 67smw,iwmax oto + 7o"c - 6soc to + 15o"c " " " " " " " " - 55c to + 125"<: " packageoption5 24-pin dip " hy24c notes 'le.st significant bit (lsb). . 2 absolute accuracy error includes gain, offset, linearity, noise and all other errors and is specified. without adjustment. 'fsr is full scale range and is 20 v for'" 10 range. 'the ad3860's analog ourputwill follow its digital inputwben register enable isalogic "0". digital input date will be latched and analog output voltage constant when register enable is a logic" 1". 'see section 19 for package oudine information. .. "sameasAD3860K. specifications subject to change without notice. vnl i q-qd nlr.itaj - tn-anal nr. r.nnv~rtf=r.c:: absolute maximum ratings + is volt supply (pin 22) . . . . .. + 18v -is volt supply (pin 14) . . . . .. -18v + 5 volt supply (pin 13) .. - o.5v to + 7v register enable (pin 19) . -o.5v to +s.5v digital inputs (pins 1-12). -o.5v to +s.5v pin configuration 24 lead dual in-line-package pin no. function 1 bit1 (msbi 2 bit2 3 bit 3 4 bit 4 5 bit5 6 bit 6 7 bit 7 8 bit8 9 bit9 10 bit 10 11 bit 11 12 bit12(lsbi 13 logic supply 14 -vs 15 vout 16 ref input 17 bipolar offset 18 10vrange 19 register enable 20 summing junction 21 common 22 +vs 23 gainaojust 24 6.3vrefout obsolete
[ applications information output voltage range selection output range 0 to + lov :t: sv :t: lov pin connection connect pin 24 to connect pin 17to - connect pin 15 to connect pin 20 to 16 21 18 nc 16 20 18 17 16 20 nc 17 input logic coding digital input msb lsb 0000 0000 0000 0000 0000 000 1 0111 1111 1111 1 000 0000 0000 1111 1111 1110 1111 1111 1111 analog output . oto+l0v :t:5v :t: lov +9.9976v +4.9976v +9.9951v +9.9951v +4.9951v +9.9902v + 5.oooov o.oooov o.oooov +4.9976v -0.oo24v -0.0049v +0.oo24v -4.9976v -9.9951v o.oooov -5.oooov -lo.oooov coding notes: i. for unipolar operation, the coding complementary straight binary (csb). 2. for bipolar operation, the coding complementary offset binary (cob). 3. for fsr = 20v, llsb = 4.88mv. 4. for fsr = joy, ilsb = 2.44mv. layout considerations proper layout and decoupling is necessary to obtain the ad3860's specified accuracy. ground (pin 21) must be tied to circuit analog ground as close to the package,as possible. grounding through a large ground plane beneath the package is preferred. power supplies should be decoupled with electrolytic or tantalum capacitors near the unit. a ij.1.f capacitor is parallel with a o.oij.1.f ceramic capacitor on all supplies is recom- mended, see figure 1. pin 22~+1sv 11'f o.o11'f pin 21 ~ground 11'ft . to.o11'f pin 1.0-4---+---1sv pin13~+sv 11'f o.o11'f pin 21 ~ ground figure 1. power supply decoupling coupling between analog and digital signals should be minimized to avoid noise pick up. use short jumpers to tie the reference output (pin 24) to the reference input (pin 16) and to tie the bipolar offset (pin 17) to the summing junction (pin 20). if the external full scale and zero adjustments are used, the series 6.8mfl resistors should be placed as close to the unit as possible. reference output the ad3860 is laser trimmed to operate from the internal 6.3 volt voltage reference. the user has the option of supplying an external reference but for specified operation the reference output (pin 24) must be connected to the reference input (pin 16). the internal reference can be used to drive an external load, but it should be buffered if load current will exceed 2.5ma. optional full scale and zero ( - full scale) adjustments the ad3860 will operate as specified without adjustment, however, absolute accuracy error can be reduced to :t: llsb by trimming as described below. adjustments should be made after warmup. as shown in figures 2 and 3 the zero -l .full scale t range of gain adj ~ < a: ... ..j < ii! ..j ..j range &c . ~ offset adj 11 . -r-allbits-1 l,?!!,set adj translates the line 'i i i i i i i all bits-n- figure 2. relationship of offset and gain adjustments for a unipolar dia converter (input, horizontal; output, vertical)' i range of offset ad~ j... . ~ange of - gain adj gain adj rotates the line all bits-1 t-++-1 1-+--+4 all b,ts-o i_full scale .- figure 3. relationship of offset and gain adjustments for a bipolar dia converter (input, horizontal; output, vertical) (-full scale) adjustment should be made before the full scale adjustment. we recommend multiturn potentiometers with maximum temperature coefficients of l00ppmf'c. series, resistors can be :t: 20% carbon composition or better. if these adjustments are not used pins 20 and 23 should not be grounded. zero ( - full scale) adjustment connect the potentiometer as shown and apply all "is" to the digital inputs. adjust the potentiometer until the analog output is equal to zero volts for unipolar output ranges and minus full scale for bipolar output ranges. +1sv 6.8mh ! 10kh ,... "! 10~~fi -1sv rangeofzero(-f.s.)adjustment = :!:o.2%fsr pin 200 digital-to-analog converters vol. 1,9-95 obsolete
full scale adjusbnent connect the potentiometer as shown and apply all "os" to the digital inputs. adjust the potentiometer for maximum chosen analog output. +15v 6.8mu j 10ku au to pin 23 0 1. ... r l00ku o.o1~f i optional -15v range of gain if.s.i adjustment = o.35%fsr register enable when the register enable (pin 19) is high (hold mode) the digital data in the input register will be latched. when the register enable is low (track mode) the converter's output will follow its input. to latch new digital data into the register, the register enable must go low for a minimufil of 6ons and the digital input data must be valid for a minimum of 4ons before the register enable goes high again. see the timing diagram below. register enable digital input data output voltage timing notes: tooepw miminum enable pulse width is60ns. t""" minimum setup time digital input. data to enable is 4ons. hold time is deaned as the required delay between the leading edge of register enable and the end ofvaud input data. the hold time is zero for the ad3860. output settung time for a 20 volt change to % 112lsb is 7"5 max. figure 4. input register timing diagram tt. to.. 8-bit microprocessor interface whenever a 12-bit dac is loaded from an 8-bit bus, two write . cycles are required. the organization most often used is "right justified." right-justified data calls for the eight least significant bits to occupy one byte, with the four most significant bits' residing in the lower half of another byte. this organization simplifies integer arithmetic. figure 5 shows an addressing byte { lo address frdm decoder hi register enable wii figure 5. right-justified 8-bit bus interface scheme for the ad3860 set up for right justified data in an 8-bit system. the four msbs are latched into the 74ls75 latch in the first write cycle. the entire 12-bit word is then loaded into the ad3860's internal input storage register on the next write cycle. an alternate scheme is to use an eight-bit intermediate register, "'" , ~~". ~.'"', or" """"--- '""","'cn""""o~ such as the 74ls373, to allow the user to load the lower order bits in the first write cycle. left-justified data can be similarly a~commodated. the overlap- ping of data lines is reversed as shown in figure 6. the ad3860 ad3860 byte { lo address from decoder hi register enable wii figure 6. left-justified 8-bit bus interface still occupies two adjacent locations in the processor's memory map. a left-justified format is convenient in applications when the data represents a 12-bit binary fraction (between 0 and 4095 ) 4096 . left-justified data has the four least significant bits in the upper half of the first byte and the eight most significant bits in the second byte. the four lsbs on the intermediate latch and the eight msbs on the data bus are all latched into the ad3860s latch simultaneously. this double buffering technique avoids the analog output slewing to an undesirable state determined by the msbs of the new digital data and the lsbs of the previous digital data. . .' many of the popular microprocessor families include components specifically designed to ease the interface between the micropro- cessor and a peripheral device such as a converter. these com- ponents are called programmable peripheral interface (ppi), peripheral interface adaptor (pia), parallel i/o controller (pio), or similar names. they typically feature two or more 8- bit wide parallel data ports which can, under program control, be configured as either inputs or outputs. their control signals are made compatible with the particular processor they serve, and in many systems can provide an attractive alternative to a collection of random logic. for example, the 8255 ppi has two 8-bit and two 4-bit ports which can be used as input, as output, or as a combination of input, output, and control. each of the 4-bit words can be grouped with one of the 8-bit words so that the interface is split into two 12-bit ports. the ports can be set up as outputs, under program control, for controlling two ad3860s with a single ppi. the 8255 contains two bits of address input: . that is, ao and al of the 8255 are driven directly by the address bus, and these bits need not be used by the address decoder. though the 8255 is an 8080 system component, it is adaptable to other ilp systems. using the ad3860 with 12- and 16-bit buses the ad3860 is easily interfaced to 12- and 16-bit data buses. the ad3860's register enable signal can usually be derived by nanding the desired address lines with the processor's mem- ory write or i/o write line. for most processors, valid data remains on the data bus for some time after either the valid address or control signals are removed. therefore, the data is latched into the ad3860 immediately after one of the address or control signals changes but before valid data goes away. the ad3860 thus occupies a single memory location. d7 do os =i do bus d3 d2 d1 do d7 do os from do data bus d3 d2 d1 do obsolete
|
